1. Field of the Invention
The present invention relates to the manufacture of high performance VLSI semiconductor chips in general and, more particularly, to a method for producing coplanar multi-level metal/insulator films on a substrate according to a chem-mech polishing technique by which conductive lines as well as stud via metal contacts are simultaneously formed.
2. Description of Prior Art
A semiconductor chip consists of an array of devices whose contacts are interconnected by patterns of wiring metal stripes. In VLSI chips, these metal patterns are multi-layered and separated by layers of insulating material. Interconnections between different levels of metal wiring patterns are made by holes (or via holes), which are etched through said layers of insulating material. Typical chip designs consist of one or two wiring levels, with three wiring levels being the current state of the art. Circuit cost and performance requirements continue to place demands on the fabrication processes in such a way that the addition of supplementary wiring levels must remain competitive even though additional processing steps are involved. However, the existing technique of using via-holes has multiple limitations and drawbacks in that, as the number of metallization layers increases, wiring becomes increasingly difficult, as may be clearly understood from FIG. 1.
The semiconductor structure 10 shown in FIG. 1 is a typical example of said current state of the art technlogy. It is comprised of a silicon substrate 11 of a predetermined conductivity type having a patterned first insulating layer 12 of silicon dioxide (SiO.sub.2) thereon. The first level of metallization is represented by a metal land 13 which makes contact through via hole 14 with a region 15 of the substrate. It makes contact, for example as an ohmic contact, with the emitter region of a bipolar transistor (not represented).
The second level of metallization represented by metal land 16 makes an electrical contact with metal land 13 through via hole 17 of the second insulating layer 18. The structure is passivated with a third insulating layer 19. Although the structure depicted in FIG. 1 is not to scale, it exemplifies the very irregular surface, far from planar, which results from the standard process.
With such a non-planar structure, the known problems are: first a risk of a potential short at location A between the first and second levels of metallization, due to the thinning of the insulating layer therebetween, and second the risk of a potential open circuit at location B, due to the thinning of the metal layer at that location (so called necking effect). Those risks are unacceptable for the high standard of reliability which are required in that industry. Therefore there is a present and serious need to improve the via-hole technique to solve the acute problem of planarizing such irregular surfaces.
Separate processes typically are used for making a given patterned metal level and for making stud via connections from the given level to a latter formed overlying patterned metal level. One example of such processes is described in Process for Multilayer Metal Technology, by G. T. Chiu et al., IBM Technical Disclosure Bulletin, Vol. 25, No. 10, March 1983, pg. 5309. According to the described technique, a lower level metal contact or conductive pattern is formed in an insulator layer, stud connectors are fabricated at selected locations of the lower level metal pattern, insulator material is placed about the stud connectors, an overlying insulator layer is deposited and patterned, and an upper level metal or other conductive pattern is placed in the overlying insulator layer. Not only is the cited technique complicated and costly but the planarization of the individual metal and stud levels is difficult to accomplish.